A Method to Analyze Aging Effect on ESD Protection Design

A 3.3V active ESD protection circuit is designed with a 16nm Fin-FET process through cascoding 1.8V FETs. The design is constrained by the lack of 3.3V FETs and the poor snapback characteristics of 1.8V FETs. The design is evaluated through circuit-level aging simulation to verify operational safety...

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Bibliographic Details
Published in2020 IEEE International Reliability Physics Symposium (IRPS) pp. 1 - 6
Main Author Meng, Kuo-Hsuan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2020
Subjects
Aging
bathtub curve
burn-in (BI)
circuit-level aging simulation
Degradation
early life failure rate (ELFR) test
electrostatic discharge (ESD)
Field effect transistors
high temperature operational life (HTOL) test
high voltage stress test (HVST)
hot-carrier injection (HCI)
infant mortality
Integrated circuit reliability
lifetime operation (OP)
mismatch
negative-bias temperature instability (NBTI)
Reliability engineering
Safety
stacked active ESD clamp
stacked ESD trigger circuit
Voltage
wear-out
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Summary:A 3.3V active ESD protection circuit is designed with a 16nm Fin-FET process through cascoding 1.8V FETs. The design is constrained by the lack of 3.3V FETs and the poor snapback characteristics of 1.8V FETs. The design is evaluated through circuit-level aging simulation to verify operational safety, and validated by the fact that there is no sign of degradation in circuit-level behavior under realistic aging profiles.
ISSN:1938-1891
DOI:10.1109/IRPS45951.2020.9129333