Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test

Power induced over-testing typically occurs when fully functional chips failed during testing because of excessive IR-drop and/or power supply noise caused by scan-based at-speed test patterns. Over the years, this problem has been tackled by either improving automatic test pattern generation (ATPG)...

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Bibliographic Details
Published in2022 IEEE International Test Conference (ITC) pp. 446 - 455
Main Authors Srivastava, Ankush, Abraham, Jais
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2022
Subjects
At-speed Test
Automated Test Pattern Generation (ATPG)
Capture Power
Local HotSpot
Low Power Test
Measurement
Object recognition
Partitioning algorithms
Power supplies
Power-aware Test
Sensors
Silicon
Switches
Voltage Droop
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Summary:Power induced over-testing typically occurs when fully functional chips failed during testing because of excessive IR-drop and/or power supply noise caused by scan-based at-speed test patterns. Over the years, this problem has been tackled by either improving automatic test pattern generation (ATPG) algorithms or low power design-for-test (DFT) techniques that typically requires hardware changes. The paper presents a methodology to address the excessive voltage droop during at-speed transition delay fault testing. A partition-based low capture power adaptive test procedure is proposed in three steps. First, identification of the physical partitions of local hot spots, Second, extract partition-based low capture power constraints. Third, the extracted constraints are given to the ATPG engine for generating at-speed patterns that satisfy the local hot spots power constraints, while minimizing the pattern count increase. Post-silicon Vmin measurements on various designs illustrates the effectiveness of the proposed solution.
ISSN:2378-2250
DOI:10.1109/ITC50671.2022.00052