Transport Triggered near Memory Accelerator for Deep Learning

As throughput of neural network accelerator datapaths have grown, memory has consistently fallen behind. Although attempts have been made to improve performance of neural networks via approaches such as batching, several layers often starve for memory bandwidth when used for tasks such as online inf...

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Bibliographic Details
Published in2021 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
Main Authors Madhu, Kavitha, Das, Saptarsi, Tyagi, Abhishek, Deshwal, Ankur, Song, Joonho, Lee, Seungwon
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2021
Subjects
Bandwidth
Mobile handsets
Neural networks
Performance evaluation
Task analysis
Throughput
VLIW
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Summary:As throughput of neural network accelerator datapaths have grown, memory has consistently fallen behind. Although attempts have been made to improve performance of neural networks via approaches such as batching, several layers often starve for memory bandwidth when used for tasks such as online inferencing. In order to mitigate memory bandwidth limitations, we propose a near memory accelerator for mobile devices based on Transport-Triggered Architecture (TTA) and evaluate its performance benefits compared to the existing approaches. Through experiments we demonstrate that our proposed accelerator achieves up to 4.3× speedup with respect to a non-near memory accelerator and the proposed TTA data-path achieves area and energy efficiency close to fixed-function datapaths while offering programmability similar to VLIW cores.
ISBN:9781728192017
1728192013
ISSN:2158-1525
2158-1525
DOI:10.1109/ISCAS51556.2021.9401315