A Multi-Polynomial CRC Circuit for 5G Standard Using Parallel Pipelining Architecture

This paper proposed a novel parallel pipelining multi-polynomial CRC circuit for high speed data calculation in 5G wireless communication while remaining efficient hardware resource usage, which can dynamically switch calculation between multiple CRC polynomials. The proposed CRC circuit is designed...

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Bibliographic Details
Published in2021 Cross Strait Radio Science and Wireless Technology Conference (CSRSWTC) pp. 307 - 309
Main Authors Pan, Jia-Hao, Zhong, Shida, Zhang, Peichang, Yuan, Tao
Format Conference Proceeding
LanguageEnglish
Published IEEE 11.10.2021
Subjects
5G mobile communication
5G wireless communication
Cyclic Redundancy Check (CRC)
Data processing
FPGA
Hardware
Parallel pipelining architecture
Switches
VHDL
Wireless communication
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Summary:This paper proposed a novel parallel pipelining multi-polynomial CRC circuit for high speed data calculation in 5G wireless communication while remaining efficient hardware resource usage, which can dynamically switch calculation between multiple CRC polynomials. The proposed CRC circuit is designed using VHDL and synthesis results are valided on Altera (Intel) Stratix IV FPGA (EP4SGX230KF40C2).
ISSN:2377-8512
DOI:10.1109/CSRSWTC52801.2021.9631619