Modeling Soft-Error Reliability Under Variability

• Published in: 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) pp. 1 - 6
• Main Authors: Balakrishnan, Aneesh, Medeiros, Guilherme Cardoso, Gursoy, Cemil Cem, Hamdioui, Said, Jenihhin, Maksim, Alexandrescu, Dan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 06.10.2021
• Subjects: Aging; Analytical models; Data models; Negative bias temperature instability; Thermal variables control; Very large scale integration; Voltage
• ISSN: 2765-933X
• DOI: 10.1109/DFT52944.2021.9568295

The Soft-Error (SE) reliability and the effects of Negative Bias Temperature Instability (NBTI) in deep submicron technologies are characterized as the major critical issues of highperformance integrated circuits. The previous scientific research studies provide a comprehensive description that the soft-error vulnerability becomes more severe as the circuit performance degrades with aging. The main reason is the reduction of cell-level critical charge in an aging environment. However, such increased soft-error generation does not necessarily contribute towards circuits' critical functional failures. The proposal of this paper is the experimental investigation of soft error propagation at the aged gate-level by considering the different derating factors like Electrical Derating (EDR), Temporal Derating (TDR), Logical Derating (LDR), and Functional Derating (FDR). As contrary to the previous studies, the results of this work prove that SEU fault propagation probability is reducing in critical paths as time advances while the propagation probability of SET faults is neither reducing nor increasing, but the spot of generation of failure enhancing SETs is shifting within the clock period.