A 2.5-V 8-Bit Low power SAR ADC using POLC and SMTCMOS D-FF for IoT Applications

• Published in: 2020 International Conference on Inventive Computation Technologies (ICICT) pp. 1097 - 1103
• Main Authors: Prathiba, G., Santhi, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2020
• Subjects: Circuits; Computer architecture; Force; Internet of Things; Leakage Power; Metals; Principled Open Loop Comparator (POLC) and Switched Multi-Threshold Complementary Metal Oxide Semiconductor (SMTCMOS); Propagation delay; Shift registers; Successive Approximation Register (SAR); Switches; Systematics
• DOI: 10.1109/ICICT48043.2020.9112548

A 2.5-V 8-bit low force and efficient Successive-Approximation Register Analog-to-Digital converter (SAR-ADC) utilizing a Principled Open Loop Comparator (POLC) and Switched Multi-Threshold Complementary Metal Oxide Semiconductor (SMTCMOS) D-FF shift Register. In light of high proficiency and low force applications SAR-ADC is increasingly well known, yet it experience the ill effects of resolution and speed confinements. To defeat the above issue proposed a systematic methodology uses low force POLC based SAR-ADC is structured. Considering about the resolution, speed and compact design of 8-bit SAR-ADC, the proposed POLC strategy reasonably diminishes the propagation delay by 37% and decreases the force utilization by 62% appeared differently in relation to the standard system. A D-flip flop is planned to employ SMTCMOS procedure which has low force utilization and productively decline the leakage power. All the above circuits are simulated by using TANNER-EDA tool in 0.25μm CMOS technology produces 97% Efficiency.