FPGA test and coverage

This paper presents an FPGA test and coverage methodology. BIST and "shift register" styles of test are discussed. Gate level fault grading results are then presented. Use of an "iterative logic unit" and its impact on test and fault grading is discussed.

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Bibliographic Details
Published inProceedings - International Test Conference pp. 599 - 607
Main Authors Toutounchi, S., Lai, A.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 2002
Subjects
Application specific integrated circuits
Applied sciences
Circuit faults
Circuit properties
Circuit testing
CMOS technology
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Field programmable gate arrays
Logic design
Logic testing
Shift registers
Software tools
Testing, measurement, noise and reliability
Transceivers
Shift register
Iterative method
Field programmable gate array
Built in self test
Impact test
Defect detection
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Summary:This paper presents an FPGA test and coverage methodology. BIST and "shift register" styles of test are discussed. Gate level fault grading results are then presented. Use of an "iterative logic unit" and its impact on test and fault grading is discussed.
ISBN:9780780375420
0780375424
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2002.1041811