Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips

• Published in: Proceedings - International Test Conference pp. 1103 - 1110
• Main Authors: Goel, S.K., Vermeulen, B.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Applied sciences; Clocks; Data analysis; Design for disassembly; Design. Technologies. Operation analysis. Testing; Digital integrated circuits; Electronics; Exact sciences and technology; Flip-flops; Integrated circuit modeling; Integrated circuits; Laboratories; Needles; Pins; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Sequential circuit; Data analysis; Multiple system; Detector circuits; Integrated circuit; Debugging; System on a chip; Clock; Flip flop circuits; Bistability
• ISBN: 9780780375420; 0780375424
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.2002.1041867

To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The state of the flip-flops and the memory elements is observed and compared with the simulation results. If the chip contains multiple clock domains then these clock domains must be stopped simultaneously, otherwise some of the elements in one or more of the clock domains will capture old data. The phenomenon of capturing old data is called data invalidation. This paper describes the data invalidation problem in depth and presents a data invalidation detector circuit. An automated hierarchical data invalidation analysis tool named DIAna is also presented. By means of experimental results for two industrial SoCs, we show the amount of data invalidation that can occur during silicon debug.