High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips

Test vehicles of various types that aim to identify yield detractors are essential for maturing a new semiconductor process before high volume production. Due to large number of unpredictable geometries created by place-and-route, test vehicles that focus on random logic are of the utmost importance...

Full description

Saved in:
Bibliographic Details
Published in2020 IEEE International Test Conference (ITC) pp. 1 - 10
Main Authors Liu, Zeye, Shawn Blanton, R. D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2020
Subjects
Arrays
Fabrication
Geometry
Germanium
Logic arrays
Logic testing
Two dimensional displays
Online AccessGet full text

Cover

More Information
Summary:Test vehicles of various types that aim to identify yield detractors are essential for maturing a new semiconductor process before high volume production. Due to large number of unpredictable geometries created by place-and-route, test vehicles that focus on random logic are of the utmost importance. Prior work that utilizes a two-dimensional regular array of logic blocks has demonstrated significant superiority over conventional approaches. In this work, a third dimension is added to ensure efficient diagnosis of multiple defects that frequently occur within a high defect-density environment. Experiments demonstrate a significant improvement in perfect diagnoses over the two-dimensional LCV.
ISSN:2378-2250
DOI:10.1109/ITC44778.2020.9325244