A study of multi-stack silicon-direct wafer bonding for MEMS manufacturing

• Published in: Proceedings, IEEE micro electro mechanical systems pp. 407 - 410
• Main Authors: Miki, N., Zhang, X., Khanna, R., Ayon, A.A., Ward, D., Spearing, S.M.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Annealing; Applied sciences; Chemical processes; Chemical technology; Electronics; Etching; Exact sciences and technology; Fabrication; Geometry; Micro- and nanoelectromechanical devices (mems/nems); Microelectromechanical devices; Micromechanical devices; Microstructure; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Wafer bonding; Manufacturing process; Microelectromechanical device
• ISBN: 0780371852; 9780780371859
• ISSN: 1084-6999
• DOI: 10.1109/MEMSYS.2002.984289

Multi-stack wafer bonding is one of the most promising fabrication techniques for creating three-dimensional microstructures, such as for power MEMS devices. However, there are several bonding issues that MEMS technologists have to face and overcome to successfully build multilayered structures. Among these are: (1) Chemical residues on surfaces to be bonded originating from the fabrication processes prior to bonding, (2) Increased stiffness due to multiple bonded wafers and/or thick wafers, (3) Bonding tool effects, and (4) Defect propagation to other wafer levels after high-temperature annealing cycles. The problems and the solutions presented here are readily applicable to any MEMS project involving the fabrication of multi-stack structures of two or more wafers containing intricate geometries and large etched areas.