An experimental study of temperature influence on electrical characteristics of ferroelectric P(VDF-TrFE) FETs on SOI

We report on the fabrication and electrical characterization of ferroelectric FETs (Fe-FET) on fully depleted SOI. The transistor gate stack is made by a 45 nm P(VDF-TrFE) 70%-30% layer on top of 10 nm thermal SiO 2 . The improved junction leakage control in thin SOI enables the accurate investigati...

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Bibliographic Details
Published in2009 Proceedings of the European Solid State Device Research Conference pp. 97 - 100
Main Authors Salvatore, G.A., Lattanzio, L., Bouvet, D., Ionescu, A.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2009
Subjects
Dielectric substrates
Electric variables
Ferroelectric materials
FETs
Hysteresis
MOSFETs
Silicon
Switches
Temperature dependence
Temperature distribution
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Summary:We report on the fabrication and electrical characterization of ferroelectric FETs (Fe-FET) on fully depleted SOI. The transistor gate stack is made by a 45 nm P(VDF-TrFE) 70%-30% layer on top of 10 nm thermal SiO 2 . The improved junction leakage control in thin SOI enables the accurate investigation of the electrical DC characteristics of Fe-FETs in a range of temperature from 25degC up to 90degC. Reductions of the non-saturated hysteretic loop and of I on /I off are observed at high temperature but the Fe-FET remarkably maintains basic switch functionality with I on /I off > 10 5 up to 85degC. We particularly report and explain the parabolic dependence of the SOI Fe-FET subthreshold swing, SS, on the temperature, featuring an experimental minimum.
ISBN:9781424443512
1424443512
ISSN:1930-8876
DOI:10.1109/ESSDERC.2009.5331330