Defect aware X-filling for low-power scan testing

Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads to lower defect coverage than random-fill. We propose a unified low-power and defect-aware X-filling method for scan test...

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Bibliographic Details
Published in2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) pp. 873 - 878
Main Authors Balatsouka, S, Tenentes, V, Kavousianos, X, Chakrabarty, K
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2010
Subjects
Automatic test pattern generation
Circuit faults
Circuit simulation
Circuit testing
Computational modeling
Computer science
Energy consumption
Fault detection
Filling
Power engineering computing
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Summary:Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads to lower defect coverage than random-fill. We propose a unified low-power and defect-aware X-filling method for scan testing. The proposed method reduces shift power under constraints on the peak power during response capture, and the power reduction is comparable to that for the Fill-Adjacent X-filling method. At the same time, this approach provides high defect coverage, which approaches and in many cases is higher than that for random-fill, without increasing the pattern count. The advantages of the proposed method are demonstrated with simulation results for the largest ISCAS and the IWLS benchmark circuits.
ISBN:1424470544
9781424470549
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2010.5456928