High-performance implementation of in-network traffic pacing

• Published in: 2011 IEEE 12th International Conference on High Performance Switching and Routing pp. 9 - 15
• Main Authors: Hanay, Y. S., Dwaraki, A., Wolf, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2011
• Subjects: Degradation; field-programmable gate array; prototyp; small-buffer network; traffic burstiness; traffic pacing
• ISBN: 9781424484546; 1424484545
• ISSN: 2325-5552
• DOI: 10.1109/HPSR.2011.5985997

Optical packet switching networks promise to provide high-speed data communication and serve as the foundation of the future Internet. A key technological problem is the very small size of packet buffers that can be implemented in the optical domain. Existing protocols, for example the transmission control protocol, do not perform well in such small-buffer networks. To address this problem, we have proposed techniques for actively pacing traffic to ensure that traffic bursts are reduced or eliminated and thus do not cause packet losses in routers with small buffers. In this paper, we present the design and prototype of a hardware implementation of a packet pacing system based on the NetFPGA system. Our results show that traffic pacing can be implemented with few hardware resources and without reducing system throughput. Therefore, we believe traffic pacing can be deployed widely to improve the operation of current and future networks.