A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme

Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper pres...

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Bibliographic Details
Published inIEEE Custom Integrated Circuits Conference 2006 pp. 301 - 304
Main Authors Pagiamtzis, K., Azizi, N., Najm, F.N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2006
Subjects
Alpha particles
CADCAM
Computer aided manufacturing
Delay
Error correction codes
Hamming distance
Integrated circuit technology
Neutrons
Power dissipation
Single event transient
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Summary:Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a binary content-addressable memory (CAM) design with high immunity to SEUs. Conventionally, error-correcting codes (ECC) have been used in SRAMs to address this issue, but these techniques are not immediately applicable to CAMs because they depend on processing the full contents of the memory word outside the array, which is not possible in a normal CAM access. The proposed design consists of a new matching technique that uses coding to increase the Hamming distance between words, in conjunction with a modified matchline sensing scheme. The result is a CAM design that reduces the SER with no increase in delay or power dissipation, and with only a 12% increase in area
ISBN:1424400759
9781424400751
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2006.320887