Topological characteristics of logic networks generated by a graph-based methodology

Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization p...

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Bibliographic Details
Published in2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) pp. 343 - 346
Main Authors Cardoso, Maicon Schneider, Zanandrea, Regis, de Souza, Renato Souza, da Silva Machado, Joao Junior, da Rosa, Leomar Soares, de Souza Marques, Felipe
Format Conference Proceeding
LanguageEnglish
Published IEEE 11.04.2016
Subjects
Benchmark testing
Boolean functions
Circuits and systems
duality
graph-based methodology
Kernel Finder
Layout
Network topology
non-series-parallel
planarity
Topology
Transistors
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Summary:Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts directly in the layout. This paper presents a methodology to identify these aspects in order to guide the cell layout generation. The results were performed over a set of intensively used benchmarks and pointed that 67.69% of the investigated networks presents a planar topology, while 21.85% shows a different number of transistors between its logic plans and 93.73% of the physical cells will contain at least one gap in its diffusion areas.
DOI:10.1109/LASCAS.2016.7451080