A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

Correct estimation of symbol timing, Carrier Frequency Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial in Orthogonal Frequency Division Multiplexing (OFDM) communication. Typically, high estimation accuracy is desired, but often comes with increased complexity. Which has a direct repercussi...

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Bibliographic Details
Published in2015 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2984 - 2987
Main Authors Diaz, Isael, Siyu Tan, Yun Miao, Wilhelmsson, Leif, Edfors, Ove, Owall, Viktor
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2015
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Summary:Correct estimation of symbol timing, Carrier Frequency Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial in Orthogonal Frequency Division Multiplexing (OFDM) communication. Typically, high estimation accuracy is desired, but often comes with increased complexity. Which has a direct repercussion in energy consumption. In this article, an architecture based on Sign-Bit estimation with low complexity, and hence low power dissipation, is presented. The architecture, is capable of estimating the afore-mentioned parameters in virtually any OFDM standard. The proof of concept has been fabricated in 65nm CMOS technology with low-power high-VT cells. Measurements performed with supply voltage of 1.2V. resulted in a power dissipation of 350 μW, 6 times smaller to that of an equivalent 8-bit architecture, and the lowest power density reported in literature.
ISBN:9781479983919
1479983918
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2015.7169314