Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS

A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing...

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Bibliographic Details
Published in2015 IEEE Asian Solid-State Circuits Conference (A-SSCC) pp. 1 - 4
Main Authors Mohammadi, Babak, Rodrigues, Joachim
Format Conference Proceeding
LanguageEnglish
Published IEEE 19.01.2016
Subjects
Capacitors
Charge pumps
Clocks
Delays
Energy dissipation
Frequency measurement
Transistors
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Summary:A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage, the proposed architecture reaches higher voltages compared to the competitive architectures when driving capacitive loads. The design is manufactured in a 65 nm technology, and measurement results confirm a 120% higher voltage compared to the conventional Dickson CP at 400 mV with identical area cost. The measured minimum operating voltage and highest charge pumping efficiency are 290 mV and 86%, respectively.
DOI:10.1109/ASSCC.2015.7387491