Integration of III-V nanowires on Si: From high-performance vertical FET to steep-slope switch

In this paper, we present recent progress in the integration of vertical III-V nanowire-channels on Si by selective-area epitaxy and demonstrations of high-performance III-V vertical surrounding-gate transistors with high-k dielectrics with an EOT of less than 1 nm, modulation doping technique, and...

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Bibliographic Details
Published in2013 IEEE International Electron Devices Meeting pp. 4.1.1 - 4.1.4
Main Authors Tomioka, Katsuhiro, Yoshimura, Masatoshi, Nakai, Eiji, Ishizaka, Fumiya, Fukui, Takashi
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.12.2013
Subjects
Circuits
Dielectrics
Heterojunctions
Indium gallium arsenide
Logic gates
Nanostructure
Nanowires
Silicon
Switches
Switching
Transistors
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Summary:In this paper, we present recent progress in the integration of vertical III-V nanowire-channels on Si by selective-area epitaxy and demonstrations of high-performance III-V vertical surrounding-gate transistors with high-k dielectrics with an EOT of less than 1 nm, modulation doping technique, and challenges in steep subthreshold-slope switching using III-V nanowire/Si heterojunctions as building blocks for low power circuits.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
ObjectType-Feature-3
content type line 23
SourceType-Conference Papers & Proceedings-2
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2013.6724557