Three Parallel Generation of a 4-Bit M-Sequence Using Single-Flux-Quantum Digital Circuits

• Published in: 2015 15th International Superconductive Electronics Conference (ISEC) pp. 1 - 3
• Main Authors: Mizugaki, Yoshinao, Mutoh, Yasuaki, Urai, Yoshiaki, Sawada, Kazunao, Watanabe, Tomoki
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2015
• Subjects: Clocks; Generators; Josephson junctions; Libraries; Niobium; Shift registers; Testing
• DOI: 10.1109/ISEC.2015.7383487

Maximum-length sequences (M-sequences) are known as pseudo random numbers generated with relatively simple digital circuits. In this paper, we present a 4-bit M-sequence generator designed and fabricated using a single-flux-quantum (SFQ) logic library and a niobium integration technology. To enhance its generation rate, we have introduced a parallelization scheme where three bits are simultaneously generated in one clock operation. The circuit comprises three exclusive ORs, one delay flip-flop, two dc/SFQ converters (for SET and CLOCK signals), and three SFQ/dc converters (for three parallel outputs). A 10-GHz clock generator of 13 bits is also implemented for high speed testing. The total number of Nb/AlOx/Nb Josephson junctions is 568. Verilog simulation has demonstrated correct circuit operation at 20-GHz clock, which corresponds to the generation rate of 60 Gb/s. The measurement was carried out in a liquid helium bath with double μ-metal cans. Low speed testing with a 1-kHz clock demonstrated periodic signals of three parallelized 4-bit M-sequence; (0, 1, 0), (1, 1, 1), (1, 0, 0), (0, 1, 0), and (0, 1, 1), where (out1, out2, out3) represents the signals from the output ports. We also confirmed that the output signals were correctly shifted when 10-GHz clocks of 13 bits were fed between two 1-kHz clock signals.