A 16nm FinFET CMOS technology for mobile SoC and computing applications

• Published in: 2013 IEEE International Electron Devices Meeting pp. 9.1.1 - 9.1.4
• Main Authors: Shien-Yang Wu, Lin, C. Y., Chiang, M. C., Liaw, J. J., Cheng, J. Y., Yang, S. H., Liang, M., Miyashita, T., Tsai, C. H., Hsu, B. C., Chen, H. Y., Yamamoto, T., Chang, S. Y., Chang, V. S., Chang, C. H., Chen, J. H., Chen, H. F., Ting, K. C., Wu, Y. K., Pan, K. H., Tsui, R. F., Yao, C. H., Chang, P. R., Lien, H. M., Lee, T. L., Lee, H. M., Chang, W., Chang, T., Chen, R., Yeh, M., Chen, C. C., Chiu, Y. H., Chen, Y. H., Huang, H. C., Lu, Y. C., Chang, C. W., Tsai, M. H., Liu, C. C., Chen, K. S., Kuo, C. C., Lin, H. T., Jang, S. M., Ku, Y.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.12.2013
• Subjects: Channels; Density; Devices; FinFETs; High definition video; High density; Logic; Logic gates; Metals; Random access memory; Semiconductor devices; Static random access memory; Transistors
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2013.6724591

For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um 2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technology provides 2X logic density and >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To our knowledge, this is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node. Low leakage (SVt) FinFET transistors achieve excellent short channel control with DIBL of <;30 mV/V and superior Idsat of 520/525 uA/um at 0.75V and Ioff of 30 pA/um for NMOS and PMOS, respectively.