Control signal skew scheduling in RT level datapath synthesis

• Published in: 48th Midwest Symposium on Circuits and Systems, 2005 pp. 1087 - 1090 Vol. 2
• Main Authors: Obata, T., Kaneko, M.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 2005
• Subjects: Circuit synthesis; Clocks; Control system synthesis; Delay effects; Multiplexing; Processor scheduling; Registers; Sequential circuits; Signal synthesis; System performance
• ISBN: 9780780391970; 0780391977
• ISSN: 1548-3746
• DOI: 10.1109/MWSCAS.2005.1594294

To improve system performance in terms of total computation time and/or robustness to delay variation, we are going to introduce appropriate delays which differentiate the arrival times of control signals to registers and multiplexers in RT level datapath, and we propose optimization algorithm of skew for both registers and multiplexers in RT level datapath synthesis. Compared with a conventional clock scheduling for sequential circuits, our skew optimization problem in RT level datapath synthesis has the following features. (1) While clock signal for a sequential circuit is fed to each flipflop every time, control signal in RT level datapath is fed to each component only in selected (i.e., scheduled) control steps. (2) Not only control signals to registers but also control signals to multiplexers are subjects to be optimized. Our proposed skew optimization is based on the combination of the graph theoretic approach and binary search of the clock period. The skew optimization is finally incorporated into the exploration of the solution space of control step schedule and resource binding to form a skew-aware datapath synthesis system