A study of FPGA-based cluster computing by high-speed serial-link communication

With demand growing applications of Big Data and Machine Learning, an enormous amount of computational effort is required in those systems. High-performance computing systems like a data center adopts massively parallel computing that can bring them significant performance improvement. However, it f...

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Bibliographic Details
Published in2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW) pp. 401 - 405
Main Authors FAN, Ruochong, YAMAGUCHI, Yoshiki
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2020
Subjects
Bandwidth
Benchmark testing
Data centers
Field programmable gate arrays
FPGA
HSS Links
Network
Parallel processing
Routing
System-on-chip
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Summary:With demand growing applications of Big Data and Machine Learning, an enormous amount of computational effort is required in those systems. High-performance computing systems like a data center adopts massively parallel computing that can bring them significant performance improvement. However, it faces making HPC systems based on the same acceleration approach more difficult to achieve further speedup since it generally troubled by its inter-node network due to its latency and insufficient bandwidth. It means this constrains the number of computing nodes in a system, namely system scalability. This article focuses on the flexible and extensible FPGA accelerator, which is widely used in the current supercomputers and data centers. The proposed approach is a communication framework by using an FPGA system with high-speed optical connections which connect among multiple FPGAs. The proposed concept is evaluated on a prototype cluster.
DOI:10.1109/CANDARW51189.2020.00082