ELMap: Area-Driven LUT Mapping with k-LUT Network Exact Synthesis

• Published in: Proceedings - Design, Automation, and Test in Europe Conference and Exhibition pp. 1 - 7
• Main Authors: Pan, Hongyang, Zhu, Keren, Yang, Fan, Chu, Zhufei, Zeng, Xuan
• Format: Conference Proceeding
• Language: English
• Published: EDAA 31.03.2025
• Subjects: Benchmark testing; Europe; Exact synthesis of k -LUT networks; Field programmable gate arrays; Logic; Logic synthesis; LUT mapping; Optimization; Table lookup; Technology mapping
• ISSN: 1558-1101
• DOI: 10.23919/DATE64628.2025.10993190

Mapping to k -input lookup tables ( k -LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the dependency of mapping results on the inherent graph structure, often leading to suboptimal results. To address this, we present ELMap, an area-driven LUT mapping framework. It incorporates structural choice during the collapsing phase. This enables dynamic decomposition, maximizing local-to-global optimization transfer. To ensure seamless integration between the optimization and mapping processes, ELMap leverages exact k -LUT synthesis to generate area-optimal sub-LUT networks. Experiments on the EPFL benchmark suite demonstrate that ELMap significantly outperforms state-of-the-art methods. Specifically, in 6-LUT mapping, ELMap reduces the average LUT area by 8.5% and improves the area-depth-product (ADP) by 5.8%. In 4-LUT remapping, it reduces the average LUT area by 17.6% and improves the ADP by 2.4%.