Finite Element Model in LTspice of a Distributed RC-Structure Fractional-Order Capacitor Device
Fractional-order capacitors can potentially be fabricated using MOS technologies taking advantage of their distributed resistive-capacitive structure. However, there are limited models to simulate the characteristics of these designs. In this work, an equivalent circuit model to represent a finite-e...
Saved in:
Published in | Proceedings of IEEE Southeastcon pp. 1494 - 1500 |
---|---|
Main Authors | , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
22.03.2025
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | Fractional-order capacitors can potentially be fabricated using MOS technologies taking advantage of their distributed resistive-capacitive structure. However, there are limited models to simulate the characteristics of these designs. In this work, an equivalent circuit model to represent a finite-element of a MOS structure is used to assemble a hierarchical model of a complete design in LTspice. This equivalent circuit model is validated (for designs with phases of -77°, -74°, -58°, and -53° with a maximum of ±2° tolerance) against previously established matrix model representations. Using this validated model varying gate length connections (from 100% to 6.25%) caused deviations less than 0.25° supporting that this characteristic of MOS technologies is not likely to have a significant effect on fabricated designs. |
---|---|
AbstractList | Fractional-order capacitors can potentially be fabricated using MOS technologies taking advantage of their distributed resistive-capacitive structure. However, there are limited models to simulate the characteristics of these designs. In this work, an equivalent circuit model to represent a finite-element of a MOS structure is used to assemble a hierarchical model of a complete design in LTspice. This equivalent circuit model is validated (for designs with phases of -77°, -74°, -58°, and -53° with a maximum of ±2° tolerance) against previously established matrix model representations. Using this validated model varying gate length connections (from 100% to 6.25%) caused deviations less than 0.25° supporting that this characteristic of MOS technologies is not likely to have a significant effect on fabricated designs. |
Author | Prokup, Lauryn A. Freeborn, Todd J. Kubanek, David |
Author_xml | – sequence: 1 givenname: Lauryn A. surname: Prokup fullname: Prokup, Lauryn A. email: laprokup@crimson.ua.edu organization: The University of Alabama,Dept. Elec. Computer Eng.,Tuscaloosa,USA – sequence: 2 givenname: David surname: Kubanek fullname: Kubanek, David email: kubanek@vut.cz organization: Brno University of Technology,Dept. Telecommunications,Brno,Czech Republic – sequence: 3 givenname: Todd J. surname: Freeborn fullname: Freeborn, Todd J. email: tjfreeborn1@eng.ua.edu organization: The University of Alabama,Dept. Elec. Comp. Eng.,Tuscaloosa,USA |
BookMark | eNo1kM1KAzEYRaMo2Na-gYvsXE3NzySTLGXaqlAp2AruSib5gpFppmQygm_fAXV1F4d74N4puopdBITuKVlQSvTDrhvyJ5g-110UUrJywQgTixFVVFB1gea60opzKkipyuoSTagQqiBCfdygad9_EcJIScUEHdYhhgx41cIRYsavnYMWh4g3-_4ULODOY4OXoc8pNEMGh9_qYpfTYPOQAK-TsTl00bTFNjlIuDYnY0PuEl7C99i_RdfetD3M_3KG3terff1cbLZPL_Xjpgi0UrlgintlmJJU28ZXlgDjykrvpHJOjsw7o632UnBKiNUN0EaN02SjuXKC8Rm6-_UGADicUjia9HP4P4SfAfJqWy0 |
ContentType | Conference Proceeding |
DBID | 6IE 6IH CBEJK RIE RIO |
DOI | 10.1109/SoutheastCon56624.2025.10971518 |
DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering |
EISBN | 9798331504847 |
EISSN | 1558-058X |
EndPage | 1500 |
ExternalDocumentID | 10971518 |
Genre | orig-research |
GrantInformation_xml | – fundername: National Science Foundation grantid: 1951552 funderid: 10.13039/100000001 – fundername: Czech Science Foundation grantid: 23-06070S funderid: 10.13039/501100001824 |
GroupedDBID | 6IE 6IF 6IH 6IK 6IL 6IN AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP OCL RIE RIL RIO |
ID | FETCH-LOGICAL-i178t-283f8a28619cbf7c0e238c6fd68dd63f8fda9c9f653100c9be1b84846b938d523 |
IEDL.DBID | RIE |
IngestDate | Wed Apr 30 05:50:38 EDT 2025 |
IsPeerReviewed | false |
IsScholarly | true |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-i178t-283f8a28619cbf7c0e238c6fd68dd63f8fda9c9f653100c9be1b84846b938d523 |
PageCount | 7 |
ParticipantIDs | ieee_primary_10971518 |
PublicationCentury | 2000 |
PublicationDate | 2025-March-22 |
PublicationDateYYYYMMDD | 2025-03-22 |
PublicationDate_xml | – month: 03 year: 2025 text: 2025-March-22 day: 22 |
PublicationDecade | 2020 |
PublicationTitle | Proceedings of IEEE Southeastcon |
PublicationTitleAbbrev | SOUTHEASTCON |
PublicationYear | 2025 |
Publisher | IEEE |
Publisher_xml | – name: IEEE |
SSID | ssj0020415 |
Score | 2.2933846 |
Snippet | Fractional-order capacitors can potentially be fabricated using MOS technologies taking advantage of their distributed resistive-capacitive structure. However,... |
SourceID | ieee |
SourceType | Publisher |
StartPage | 1494 |
SubjectTerms | Capacitors Circuits and systems Design methodology Equivalent circuits Finite element analysis Integrated circuit modeling Logic gates |
Title | Finite Element Model in LTspice of a Distributed RC-Structure Fractional-Order Capacitor Device |
URI | https://ieeexplore.ieee.org/document/10971518 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1La8JAEF6qh9Je-rL0zR4KPW00a0w252iQ0trSKniTfUxAKolYvfTXdyZR-4BCbyGBZbMD89iZ7_sYu5XW-k63rMDwakUQghRxS0sRysgYG1lotwko_DgI-6PgftwZr8HqJRYGAMrhM_Dosezlu8Ku6KqsSd1SjFCqxmpYuVVgrW11RVjzXXa3JtFslgp0JH-TFDmmLJLuT2TH2yzxQ0yljCXpARtsdlGNkLx5q6Xx7McvgsZ_b_OQNb5ge_x5G5CO2A7kx2z_G-PgCZukU0oyea-aGuckhTbj05w_DN_n6DN4kXHNu8SmS0JY4PhLIl5LjtnVAni6qHAQeiaeiLOTJxhrLTqFBe8C-ZwGG6W9YdIXa40FMfUjtRSYXWRKS4V1lDVZZFuAMdyGmQuVcyF-y5yObZyFHeoE2NiAb1SASYuJ28phFXvK6nmRwxnj6HLbuJwJScDER1ODL7WCAE0Pkcz0OWvQWU3mFY3GZHNMF3-8v2R7ZDIa-JLyitXxX-EaM4CluSkt_wnI0LEf |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1bS8MwFA46wcuLt4l38yD4lG5N78_dytRtim6wt9KkpzAc7Zjbi7_ec9ptXkDwrbQQ0iSc7yQ53_cxdiu1NtOkqQXCqxa2C1IEzUQKV3pKaU-DZRFRuNd3O0P7YeSMlmT1kgsDAGXxGRj0WN7lp4Ve0FFZg25LEaH8TbaFwO-YFV1rvb8itvk2u1vKaDZKDzoywAmLHJMWSSco0jFWjfywUynRJNpn_VU_qiKSN2MxV4b--CXR-O-OHrD6F3GPP68h6ZBtQH7E9r5pDh6zOBpTmsnbVd04JzO0CR_nvDt4n2LU4EXGE94iPV2ywoKUv4TitVSZXcyAR7OKCZFMxBOpdvIQ0VZjWJjxFlDUqbNh1B6EHbF0WRBj0_PnAvOLzE-kjzsprTJPNwFRXLtZ6vpp6uK3LE0CHWSuQ3cBOlBgKt_GtEUFlp_iPvaE1fIih1PGMeha2JxyycLExMkGUyY-2Dj54MksOWN1Gqt4WglpxKthOv_j_Q3b6Qx63bh733-8YLs0fVT-JeUlq-F_wxXmA3N1Xa6CTzTStGg |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+IEEE+Southeastcon&rft.atitle=Finite+Element+Model+in+LTspice+of+a+Distributed+RC-Structure+Fractional-Order+Capacitor+Device&rft.au=Prokup%2C+Lauryn+A.&rft.au=Kubanek%2C+David&rft.au=Freeborn%2C+Todd+J.&rft.date=2025-03-22&rft.pub=IEEE&rft.eissn=1558-058X&rft.spage=1494&rft.epage=1500&rft_id=info:doi/10.1109%2FSoutheastCon56624.2025.10971518&rft.externalDocID=10971518 |