Ultra-Low Power Robust Digital Pulse Width Modulation Circuit for Pacemaker Telemetry

• Published in: Biomedical Circuits and Systems Conference pp. 1 - 5
• Main Authors: Li, Feifei, Xu, Jiangtao, Wang, Yuyuan, Zhang, Hong
• Format: Conference Proceeding
• Language: English
• Published: IEEE 24.10.2024
• Subjects: Codes; delay locked loop; Delays; Digtal pulse width modulation; forced locking; implantable medical devices; Multiplexing; Pacemakers; Power demand; Pulse width modulation; Robustness; Transmitters; Voltage; Wireless sensor networks
• ISSN: 2766-4465
• DOI: 10.1109/BioCAS61083.2024.10798171

In the transmitter circuit of the pacemaker, pulse width modulation (PWM) technology is applied to further reduce power consumption and adapt to process variations. The conventional method to generate adjustable pulse width is by controlling the delay through tuneable charging current. However, such technology experience large diversity when the current is greatly restricted to the level of sub- \mu \mathrm{A}. In this paper, a novel digital pulse width modulation (DPWM) circuit based on a delay-locked loop (DLL) is proposed, which, being a closedloop system, exhibits greater robustness against Process, Voltage, and Temperature (PVT) variations. To further reduce power consumption, the DLL is turned off after the locking is detected. The digital code controlling the delay chain is fixed corresponding to the required pulse width. Also, a multiplexer is used to select different pulse widths with a step of 2 \mu \mathrm{~s}. Additionally, forced locking is implemented as a backup mechanism to prevent loss of lock within the specified time. The entire circuit module is implemented in 0.35-\mu \mathrm{m} CMOS with an effective area of 433 \times 596 \mathrm{um}^{2}. The pulse width accuracy of 5.4% and a low power consumption of 0.94 \mu \mathrm{~W} under a supply voltage of 2 \sim 2.8 \mathrm{~V} are achieved, thus realizing a robust, low-power PWM circuit.