Investigation of Temperature Impacts on I-V Characteristics to Analog/RF of Drain Underlap Based L-Shaped TFET

• Published in: Proceedings of the ... IEEE Conference on Nanotechnology pp. 347 - 351
• Main Authors: Singh, Prabhat, Raman, Ashish, Kumar, Naveen, Dixit, Ankit, Kumar, Prateek, Yadav, Dharmendra Singh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 08.07.2024
• Subjects: Logic gates; Low power electronics; Performance evaluation; Radio frequency; Temperature distribution; TFETs; Voltage
• ISSN: 1944-9380
• DOI: 10.1109/NANO61778.2024.10628753

In this work, an L-shaped Tunnel FET is demonstrated for the impact of the simulation models and temperature variations. When temperature increases above the room temperature (250K to 450K), it significantly affects the carrier mobility and carrier injection process. The SRH (Shockley-Read-Hall) and TAT (Trap-assisted Tunneling) show their significance in increasing the OFF -state current (ambipolar behavior) for the lower and negative values of gate voltage. When gate voltage rises, the BTBT model (Band-to-Band-Tunneling) starts to show its presence, and the impact of SRH and TAT models starts decreasing. Because of this, the OFF -state current starts diminishing as gate voltage increases. According to the applied electric field, the BTBT, SRH, and TAT current functionalities have particular confining regions. TAT and SRH aspects predominate drain current at weak electric fields, as they are very susceptible to temperature variations. Hence, the change in models and temperature affects the device efficacy, such as analog and high-frequency functionality, and it necessitates a detailed investigation.