On Error Correction for Nonvolatile Processing-In-Memory

• Published in: 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) pp. 678 - 692
• Main Authors: Cilasun, Husrev, Resch, Salonik, Chowdhury, Zamshed I., Zabihi, Masoud, Lv, Yang, Zink, Brandon, Wang, Jian-Ping, Sapatnekar, Sachin S., Karpuzcu, Ulya R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 29.06.2024
• Subjects: Computer architecture; Energy efficiency; Error correction; Error correction codes; Nonvolatile memory; Substrates
• DOI: 10.1109/ISCA59077.2024.00055

Processing in memory (PiM) represents a promising computing paradigm to enhance performance of numerous dataintensive applications. Variants performing computing directly in emerging nonvolatile memories can deliver very high energy efficiency. PiM architectures directly inherit the vulnerabilities of the underlying memory substrates, but they also are subject to errors due to the computation in place. Numerous well-established error correcting codes (ECC) for memory exist, and are also considered in the PiM context, however, they typically ignore errors that occur throughout computation. In this paper we revisit the error correction design space for nonvolatile PiM, considering both storage/memory and computation-induced errors, surveying several self-checking and homomorphic approaches. We propose several solutions and analyze their complex performance-area-coverage trade-off, using three representative nonvolatile PiM technologies. All of these solutions guarantee single error correction for both, bulk bitwise computations and ordinary memory/storage errors.