A Sub-Sampling Front-End with 12 fF Load for On-Chip Measurements

A sub-sampling front-end with a low capacitive loading followed by a second order \Sigma\Delta ADC is presented. The front end is designed in the UMC 65nm low-power CMOS process and has a power consumption of 110 µW from a 1.2 V supply. The ADC has a simulated SQNR of around 74 dB and an ENOB of aro...

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Bibliographic Details
Published inConference proceedings : Midwest Symposium on Circuits and Systems pp. 956 - 959
Main Authors R., Aashish T., Chatterjee, Shouri
Format Conference Proceeding
LanguageEnglish
Published IEEE 11.08.2024
Subjects
Circuits and systems
CMOS process
high frequency
Loading
low capacitive loading
Power demand
sub-sampling
System-on-chip
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ISSN1558-3899
DOI10.1109/MWSCAS60917.2024.10658703

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Summary:A sub-sampling front-end with a low capacitive loading followed by a second order \Sigma\Delta ADC is presented. The front end is designed in the UMC 65nm low-power CMOS process and has a power consumption of 110 µW from a 1.2 V supply. The ADC has a simulated SQNR of around 74 dB and an ENOB of around 12 bits. The time constant of the sampling front-end comes to nearly 0.76 ps. The entire front end occupies an area of 200 µm x 550 µm.
ISSN:1558-3899
DOI:10.1109/MWSCAS60917.2024.10658703