The Impact of Nanoscale CMOS Devices Scaling and Variations on mm-Wave CMOS Performance

The impact of nanoscale CMOS devices scaling and variations as well as layout dependent effects (LDE) on high frequency performance appears as the most critical challenge to nanoscale devices optimization and modeling for mm-Wave and Sub-THz CMOS circuits simulation and design. This paper presents a...

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Bibliographic Details
Published in2024 19th European Microwave Integrated Circuits Conference (EuMIC) pp. 379 - 382
Main Authors Guo, Jyh-Chyurn, Ou, Jyun-Rong
Format Conference Proceeding
LanguageEnglish
Published European Microwave Association (EuMA) 23.09.2024
Subjects
Analytical models
CMOS
fMAX
Foundries
High frequency
Integrated circuit modeling
layout
mm-Wave
nanoscale device
Nanoscale devices
Object recognition
Optimization
Parameter extraction
PDK
Performance evaluation
scaling
Semiconductor device modeling
variations
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Summary:The impact of nanoscale CMOS devices scaling and variations as well as layout dependent effects (LDE) on high frequency performance appears as the most critical challenge to nanoscale devices optimization and modeling for mm-Wave and Sub-THz CMOS circuits simulation and design. This paper presents an extraordinary finding in sub-60 nm devices which can exactly meet the foundry golden die target in terms of IDS and g m from DC measurement on different dies/lots but exhibit dramatic differences at the high frequency performance, such as f T and f MAX . It highlights a fundamental problem with the foundry PDK (Process Design Kit) and compact models which are limited to I-V and C-V curves fitting and become invalid for high frequency simulation. For the first time, a high precision parameters extraction method and analytical models are developed based on high frequency characterization to precisely identify sub-nm or atomic scale variations in nanoscale device parameters and explain the mechanism responsible for very different impact on f T and f MAX in mm-Wave domain. This fully high frequency based method can facilitate accurate simulation and prediction of f T and f MAX subject to nanoscale devices scaling and variations.
DOI:10.23919/EuMIC61603.2024.10732380