An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs

One of the main causes of ESD failure, the Charged-Device-Model (CDM) current can cause a voltage build-up across Gate-Source junction of receiver MOS resulting in breakdown. An efficient and cost-effective solution is proposed to identify CDM risks in designs and further analyze the identified risk...

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Bibliographic Details
Published in2024 46th Annual EOS/ESD Symposium (EOS/ESD) Vol. 46; pp. 1 - 8
Main Authors Ghosh, Subhadeep, Ray, Kaustav, Sankaralingam, Raj, Pok, Rith
Format Conference Proceeding
LanguageEnglish
Published EOS/ESD Association, Inc 16.09.2024
Subjects
Breakdown voltage
Electric breakdown
Electrostatic discharges
Engines
Junctions
Logic gates
Pattern recognition
Receivers
Risk analysis
Topology
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DOI10.23919/EOS/ESD61719.2024.10702132

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Summary:One of the main causes of ESD failure, the Charged-Device-Model (CDM) current can cause a voltage build-up across Gate-Source junction of receiver MOS resulting in breakdown. An efficient and cost-effective solution is proposed to identify CDM risks in designs and further analyze the identified risks considering the full context of the design in Bulk-Silicon processes. First, simple risk topologies are used for recognition through a pattern identification engine. Those are then augmented with various risk analysis capabilities, to only highlight real risks, weeding out false violations.
DOI:10.23919/EOS/ESD61719.2024.10702132