A 1.2 GHz 5-bit RC-Based Phase Interpolator with High Linearity Achieved by Self-Centering Interpolation and Buffer Delay Matching

• Published in: Biomedical Circuits and Systems Conference pp. 1 - 5
• Main Authors: Zhang, Tong, Huo, Runtao, Mercier, Patrick P., Wang, Hui
• Format: Conference Proceeding
• Language: English
• Published: IEEE 24.10.2024
• Subjects: delay mismatch; Delays; Detectors; Digital filters; high linearity; Interpolation; Jitter; Linearity; low noise; Optimization; Parasitic capacitance; Phase interpolator; Phase locked loops; PLL; RC phase interpolator; self-centering; Semiconductor device modeling; spur
• ISSN: 2766-4465
• DOI: 10.1109/BioCAS61083.2024.10798247

High linearity phase interpolators (PIs) are becoming essential in advanced phase-locked loops (PLLs) targeting at extremely stringent jitter and spur specifications. This paper introduces a RC-based PI featuring self-centering interpolation (SCI) and buffer delay matching (BDM) techniques for linearity optimization. Through the proposed SCI technique, the detrimental extra delay in the interpolating module (IPM) due to the parasitic capacitance is compensated by intentionally introducing the same delay in the pass-through modules (PTM), allowing for self-centering of the interpolated phase. Meanwhile, a foreground calibration based on a bang-bang phase detector and a digital filter is employed to match the delay of the buffers utilized in the PI, ensuring a high-linearity square-wave generation. Designed in a 40 nm CMOS process, the proposed PI achieves a 5 bit resolution with a differential nonlinearity and an integral nonlinearity better than 0.05 LSB and 0.06 LSB, respectively, when operating with a 1.2 GHz input, and consumes a 3.2 mW power under a 1.1 V supply according to post-layout simulations.