Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

Hierarchical power distribution with a power tree has been developed. The key features are power tree management rules and a distributed common power-domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a...

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Bibliographic Details
Published in2007 IEEE International Conference on Integrated Circuit Design and Technology pp. 1 - 4
Main Authors Kanno, Y., Mizuno, H., Yasu, Y., Hirose, K., Shimazaki, Y., Hoshi, T., Miyairi, Y., Ishii, T., Yamada, T., Irita, T., Hattori, T., Yanagisawa, K., Irie, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2007
Subjects
Circuits
Clocks
Digital signal processing chips
Fabrication
Laboratories
Large scale integration
Leakage current
Power distribution
Repeaters
System-on-a-chip
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Summary:Hierarchical power distribution with a power tree has been developed. The key features are power tree management rules and a distributed common power-domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1,000,000-gate power domain were effectively reduced to 1/4,000 in multi-CPU SoCs with minimal area overhead.
ISBN:9781424407569
1424407567
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2007.4299537