Dynamically Adapted Low-Energy Fault Tolerant Processors

The constant advances on scaling have introduced several issues to the design of processing structures in new technologies. The closer one gets to nano-scale devices, the more necessary are methods to develop circuits that are able to tolerate high defect densities. At the same time, beyond area cos...

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Bibliographic Details
Published in2009 NASA/ESA Conference on Adaptive Hardware and Systems pp. 91 - 97
Main Authors Pereira, M.M., Carro, L.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2009
Subjects
Circuits
Costs
defect tolerance
dynamic reconfiguration
energy reduction
Fabrics
Fault tolerance
graceful degradation
Maintenance
Microprocessors
Nanoscale devices
on-line binary translation
Power dissipation
Process design
Redundancy
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Summary:The constant advances on scaling have introduced several issues to the design of processing structures in new technologies. The closer one gets to nano-scale devices, the more necessary are methods to develop circuits that are able to tolerate high defect densities. At the same time, beyond area costs, there is a pressure to maintain energy and power dissipation at acceptable levels, which practically forbids classical redundancy. This paper presents a dynamic solution to provide reliability and reduce energy of a microprocessor using a dynamically adaptive reconfigurable fabric. The approach combines the binary translation mechanism with the sleep transistor technique to ensure graceful degradation for software applications, while at the same time can reduce energy by shutting off the power supply of the unused and the defective resources of a reconfigurable fabric.
ISBN:0769537146
9780769537146
DOI:10.1109/AHS.2009.34