High-performance imaging subsystems and their integration in mobile devices

• Published in: 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) p. 170
• Main Authors: Lindwer, Menno, Pedersen, Mark Ruvald
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2013
• Subjects: ASIP; Graphics; Imaging; IP integration; IP networks; MPSoC; Program processors; Scheduling; Software; System-on-chip
• ISBN: 1467350710; 9781467350716
• ISSN: 1530-1591; 1558-1101
• DOI: 10.7873/DATE.2013.048

Within today's SoCs, functionality such as video, audio, graphics, and imaging is increasingly integrated through IP blocks, which are subsystems in their own right. Integration of IP blocks within SoCs always brought software integration aspects with it. However, since these subsystems increasingly consist of programmable processors, many more layers of firmware and software need to be integrated. In the imaging domain, this is particularly true. Imaging subsystems typically are highly heterogeneous, with high levels of parallelism. The construction of their firmware requires target-specific optimization, yet needs to take interoperability with sensor input systems and graphics/display subsystems into account. Hard real-time scheduling within the subsystem needs to cooperate with less stringent image analytics and SoC-level (OS) scheduling. In many of today's systems, the latter often only supports soft scheduling deadlines. At HW level, IP subsystems need to be integrated such that they can efficiently exchange both short-latency control signals and high-bandwidth data-plane blocks. Solutions exist, but need to be properly configured. However, at the SW level, currently no support exists that provides (i) efficient programmability, (ii) SW abstraction of all the different HW features of these blocks, and (iii) interoperability of these blocks. Starting points could be languages such as OpenCL and OpenCV, which do provide some abstractions, but are not yet sufficiently versatile.