Ultra thin hermetic wafer level, chip scale package

• Published in: 56th Electronic Components and Technology Conference 2006 p. 7 pp.
• Main Authors: Shiv, L., Heschel, M., Korth, H., Weichel, S., Hauffe, R., Kilian, A., Semak, B., Houlberg, M., Egginton, P., Hase, A., Kuhmann, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Application specific integrated circuits; Chip scale packaging; Costs; Handheld computers; Integrated circuit packaging; Micromechanical devices; Silicon; Surface-mount technology; Wafer bonding; Wafer scale integration
• ISBN: 1424401526; 9781424401529
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2006.1645794

This paper presents a novel technology for hermetic wafer-level chip size packaging (WLCSP). The ultra thin surface mountable (SMT) package has a small footprint and addresses MEMS and IC applications in the emerging market for handheld devices. Our approach combines through-wafer interconnects (mu-vias), wafer-to-wafer bonding, subsequent thinning and solder bumping to obtain a small form factor package. The latter adds as little as 100 mum to the final device, resulting in a total thickness of 0.5mm or less. The short interconnects enable true chip-size packages as small as 700times700 mum for direct surface mount attach. In the paper we present the packaging concept, detailed description of the process and characterization of the electrical properties and sealing