A 2.5V, 5mW UMTS and GSM dual mode decimation filter for sigma delta ADC

This paper describes a decimation processor for a dual-mode sigma-delta ADC for GSM and UMTS mobile standards. Partly contradictory requirements like high dynamic range and low bandwidth for GSM and vice versa for UMTS need decimation factors of M=144 (GSM) and M=8 (UMTS). A multi-rate filter archit...

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Bibliographic Details
Published in2007 IEEE Asian Solid-State Circuits Conference pp. 272 - 275
Main Authors Chi Zhang, Ofner, E.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2007
Subjects
3G mobile communication
Bandwidth
CMOS technology
Delta-sigma modulation
Dynamic range
Energy management
Filters
GSM
Hardware
Silicon
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Summary:This paper describes a decimation processor for a dual-mode sigma-delta ADC for GSM and UMTS mobile standards. Partly contradictory requirements like high dynamic range and low bandwidth for GSM and vice versa for UMTS need decimation factors of M=144 (GSM) and M=8 (UMTS). A multi-rate filter architecture, which allows best hardware re-use for both mobile standards, is selected. Since the ADC is to be integrated into the power management component of the mobile terminal utilizing a 0.35 mum CMOS technology, special attention has been given to silicon area and power consumption of the component, while maintaining a standard design flow for the implementation. The processor covers 1.13 mm 2 of silicon and consumes 4.72 mW in GSM and 5.54 mW in UMTS mode, both at V dd =2.5 V.
ISBN:1424413591
9781424413591
DOI:10.1109/ASSCC.2007.4425683