Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, t...

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Published in2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) pp. 330 - 335
Main Authors Coudrain, P., Colonna, J.-P, Aumont, C., Garnier, G., Chausse, P., Segaud, R., Vial, K., Jouve, A., Mourier, T., Magis, T., Besson, P., Gabette, L., Brunet-Manquat, C., Allouti, N., Laviron, C., Cheramy, S., Saugier, E., Pruvost, J., Farcy, A., Hotellier, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2012
Subjects
Assembly
Etching
Nails
Reliability
Silicon
Stacking
Through-silicon vias
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Summary:This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.
ISBN:9781467345538
1467345539
DOI:10.1109/EPTC.2012.6507102