A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning,...

Full description

Saved in:
Bibliographic Details
Published in2018 IEEE Symposium on VLSI Circuits pp. 183 - 184
Main Authors Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Staszewski, Robert Bogdan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Detectors
Jitter
Phase locked loops
Switches
Tuning
Voltage-controlled oscillators
Online AccessGet full text

Cover

More Information
Summary:All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain. We propose a hybrid-PLL in 7nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL with a periodical phase realignment by the reference clock. It covers 0.2GHz-4GHz with 0.619ps integrated jitter and settles in 0.6us.
DOI:10.1109/VLSIC.2018.8502274