A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications

• Published in: 2018 IEEE Symposium on VLSI Technology pp. 129 - 130
• Main Authors: Jerry, M., Aziz, A., Ni, K., Datta, S., Gupta, S. K., Shukla, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2018
• Subjects: Adaptive arrays; Computer architecture; Microprocessors; Nonvolatile memory; Programming; Switches; Threshold voltage
• ISSN: 2158-9682
• DOI: 10.1109/VLSIT.2018.8510679

In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO 2 to overcome the fundamental trade-off between memory window MW /read current ratio (I read,1 /I read,0 ) , and program voltage (V prog )/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (I ON /I OFF >10 7 ) - during read, the TS turns ON only if the FeFET is in the low-V T SET state, and remains OFF if the FeFET is in the high-V T RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger I read,1 /I read,0 compared to the FeFET, at iso-V prog (DC); (b) Enables 25% reduction in V prog at iso-I read,1 /I read,0 during pulse operation-facilitated by the 8× improvement in I read,1 /I read,0 ; (c) Exhibits 2.5×reduction in programming power at iso-I read,1 /I read,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.