Buffer size minimization method considering mix-clock domains and discontinuous data access

We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patter...

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Bibliographic Details
Published in2012 IEEE Asia Pacific Conference on Circuits and Systems pp. 380 - 383
Main Authors Lih-Yih Chiou, Liang-Ying Lu, Bo-Chi Lin, Su, Alan P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2012
Subjects
Computer architecture
Minimization methods
Power demand
Scheduling
Synchronization
Throughput
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Summary:We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.
DOI:10.1109/APCCAS.2012.6419051