The Failure Mode Investigation of Barrier Layer TaN Combined with Al Pad Architecture using in Cu Process

CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called "cosmetic defects" in 130- and 90-nm complementary metal-oxide-semiconduc...

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Bibliographic Details
Published in2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits pp. 263 - 266
Main Authors Po-Ying Chen, Shen-Li Chen, Ming-Hsiung Tsai, Jing, M.H., Lin, T.-C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2007
Subjects
barrier metal
Chip scale packaging
CMOS
CMOS process
Copper
Copper process
cosmetic defects
Delay
Dry etching
Electronic mail
Geometry
Manufacturing processes
Ultra large scale integration
Wiring
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Summary:CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called "cosmetic defects" in 130- and 90-nm complementary metal-oxide-semiconductor (CMOS) process node.
ISBN:1424410142
9781424410149
ISSN:1946-1542
1946-1550
DOI:10.1109/IPFA.2007.4378097