Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond

The scaling of STT-MRAM for deeply scaled nodes (e.g. sub-10 nm CMOS) requires low resistance-area-product (RA) magnetic tunnel junctions (MTJs) to contain switching voltage (V c ) and to assure high endurance. In contrast to various reports, we demonstrate systematic engineering of low-RA MTJs with...

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Bibliographic Details
Published in2018 IEEE Symposium on VLSI Technology pp. 185 - 186
Main Authors Park, C., Lee, H., Ching, C., Ahn, J., Wang, R., Pakala, M., Kang, S. H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Integrated circuits
Magnetic tunneling
Resistance
Switches
Thermal stability
Tunneling magnetoresistance
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ISSN2158-9682
DOI10.1109/VLSIT.2018.8510653

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Summary:The scaling of STT-MRAM for deeply scaled nodes (e.g. sub-10 nm CMOS) requires low resistance-area-product (RA) magnetic tunnel junctions (MTJs) to contain switching voltage (V c ) and to assure high endurance. In contrast to various reports, we demonstrate systematic engineering of low-RA MTJs without trading off key device attributes and remarkably, with higher barrier reliability. The MTJs integrate an ultra-thin synthetic antiferromagnetic layer (tSAF) with a Co/Pt pseudo-alloy pinned layer. By reducing RA from 10 to 5 Ωµm 2 , significantly reduced V c and reliable switching at 5 ns have been achieved. Furthermore, the breakdown voltage (V BD ) has been improved. The results suggest that the tunability of MTJ is extended to sub-10 nm CMOS for high-performance and high-reliability MRAM.
ISSN:2158-9682
DOI:10.1109/VLSIT.2018.8510653