Improved Test Efficiency in Cores-Based System-on-Chips Using ModelSim Verification Tool

• Published in: 2008 IEEE Instrumentation and Measurement Technology Conference pp. 1487 - 1492
• Main Authors: Das, S.R., Jun-Feng Li, Hossain, A., Nayak, A.R., Petriu, E.M., Biswas, S., Jone, W.-B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2008
• Subjects: Built-in self-test (BIST); Circuit faults; Circuit simulation; Circuit testing; Costs; Digital circuits; embedded cores-based system-on-chips (SOCs); fault injection; fault simulation; Integrated circuit technology; module under test (MUT); Software testing; System testing; System-on-a-chip; test pattern generator (TPG); Verilog HDL; Very large scale integration
• ISBN: 9781424415403; 1424415403
• ISSN: 1091-5281
• DOI: 10.1109/IMTC.2008.4547278

Due to paradigm shift from system-on-board to designs embracing embedded cores-based system-on-chips (SOCs), the complexity of digital circuits has enormously increased in recent times. This growing complexity has created a huge challenge in developing their appropriate and efficient fault testing environment. Despite enormous efforts directed towards effective testing of very large scale integrated (VLSI) circuit chips with reasonable cost, new frontiers emerged with advances in technology. The subject paper plans to develop a method to test verify circuit architecture under a hardware software co-design environment, specifically targeting embedded cores-based system-on-chips (SOCs). The concept of design-for-testability (DFT) is utilized in the paper together with ModelSim simulation and verification tool to test simulate the entire design. Some simulation results on ISCAS 85 combinational benchmark circuits are also included with a comparison of the results with some earlier works.