A comparative analysis of coarse-grain and fine-grain power gating for FPGA lookup tables

• Published in: 2009 52nd IEEE International Midwest Symposium on Circuits and Systems pp. 507 - 510
• Main Authors: Nair, P.S., Koppa, S., John, E.B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2009
• Subjects: CMOS process; CMOS technology; Coarse-grain power-gating; Field programmable gate arrays; Field-programmable gate arrays (FPGAs); fine-grain power-gating; leakage; Leakage current; low-power; Multiplexing; Power dissipation; Random access memory; Table lookup; Threshold voltage; Tunneling
• ISBN: 1424444799; 9781424444793
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2009.5236045

Leakage power dissipation is becoming a concern in field-programmable gate arrays (FPGAs) due to scaling in FPGA technology. Widely available commercial FPGAs are based on lookup tables (LUTs) consisting of SRAM arrays and multiplexers. In this paper, we analyze the leakage power dissipation in the SRAM-array of a FPGA LUT for a 65 nm CMOS process. We apply power-gating to an FPGA LUT SRAM array in two different ways, namely, coarse-grain power gating and fine-grain power gating. We carry out a comparative analysis of the two methods. In our research, we found that power-gating can be employed to drastically reduce the leakage power dissipation in the SRAM. More leakage savings were obtained with coarse-grain power-gating than with fine-grain power gating. The coarse-grain and fine-grain power-gating techniques yielded approximately 99 percent and 81 percent leakage savings, respectively, over the case where no power-gating is applied.