Data compression using mixed cascade of nonlinear logic

• Published in: 2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) pp. 1544 - 1549
• Main Authors: Das, Sunil R., Shaw, Danny L., Biswas, Satyendra N., Assaf, Mansour H., Morton, Scott, Ozkarahan, Irem, Petriu, Emil M., Groza, Voicu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2013
• Subjects: Aliasing-free (zero-aliasing) space compaction; ATALANTA; Benchmark testing; Built-in self-test; built-in self-testing in very large scale integration circuits and systems; Circuit faults; Compaction; fault detection and conditional fault detection compatibility; Integrated circuit modeling; Logic gates
• ISBN: 9781467346214; 1467346217
• ISSN: 1091-5281
• DOI: 10.1109/I2MTC.2013.6555673

The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zeroaliasing (aliasing-free) space compression hardware for single stuck-line faults, extending well-known concept of conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test (CUT), the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other pair of response data outputs being simultaneously fault detection compatible) with respect to two-input AND/NAND and/or OR/NOR logic. The process is illustrated with the design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM and COMPACTEST, though, because of space constraints, only some partial results on simulation on ISCAS 89 full-scan sequential benchmark circuits using ATALANTA are provided here.