A high density Twin-Gate OTP cell in pure 28nm CMOS process

A high density high-k gate dielectric breakdown OTP cell with a self-aligned twin-gate isolation in pure 28nm HKMG process is demonstrated. With a merged spacer isolation formed by two tiny metal gates, the OTP cells can be well isolated with an ultra small cell size of 0.0441μm 2 in pure 28nm CMOS...

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Bibliographic Details
Published inProceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) pp. 1 - 2
Main Authors Woan Yun Hsiao, Chin Yu Mei, Wen Chao Shen, Tzong Sheng Chang, Yue Der Chih, Ya-Chin King, Chrong Jung Lin
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2014
Subjects
Abstracts
CMOS integrated circuits
CMOS technology
Electric breakdown
Logic gates
Reliability
Stress
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Summary:A high density high-k gate dielectric breakdown OTP cell with a self-aligned twin-gate isolation in pure 28nm HKMG process is demonstrated. With a merged spacer isolation formed by two tiny metal gates, the OTP cells can be well isolated with an ultra small cell size of 0.0441μm 2 in pure 28nm CMOS logic process. The Twin-Gate OTP memory adopts low voltage high-k dielectric breakdown mechanism to obtain 10 4 times of On/Off ratio by a low program voltage of 4V in 20μs. A tiny and excellent Twin-Gate isolation with wide program and temperature margins has been successfully achieved in this OTP cell. Superior disturbs immunity and data retention further support the new logic OTP cell to be a promising solution in advanced logic NVM applications.
ISSN:1524-766X
2690-8174
DOI:10.1109/VLSI-TSA.2014.6839664