Electrical model analysis & measurement of TSV to TSV coupling capacitance

In order to achieve high density and high performance package, Through Silicon Vias (TSVs) technology had been developed; TSVs provide a short distance and low loss structure between different stack layers. Due to the low TSVs' yield impacting the final product significantly, the suitable test...

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Bibliographic Details
Published in2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT) pp. 294 - 297
Main Authors Shiuan-hau Yang, Hong-Pin Su, Kuang-Ching Fan, Hsin-Hung Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2013
Subjects
Capacitance
Circuit faults
Silicon
Substrates
Testing
Three-dimensional displays
Through-silicon vias
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Summary:In order to achieve high density and high performance package, Through Silicon Vias (TSVs) technology had been developed; TSVs provide a short distance and low loss structure between different stack layers. Due to the low TSVs' yield impacting the final product significantly, the suitable test method of TSVs within the process is vital to avoid products with the fault during the mass production. By virtue of the inherent capacitive characteristics, it could be detected the faulty TSVs with little area overhead for the circuit under testing. In this paper, we presented an analysis for electrical model and measurement of TSVs' coupling capacitance by different pitches. Also, we proposed the single-side test architecture and the probe technique for TSV testing. The final modeled and measured results show that this testing technique could be practically applied to the process of TSVs formation.
ISSN:2150-5934
2150-5942
DOI:10.1109/IMPACT.2013.6706652