A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET
A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE) and half-rate 10-tap decision feedback equalizer (DFE) with first tap speculative. Proposed voltage pre-shift scheme uses a programmable offs...
Saved in:
Published in | 2019 Symposium on VLSI Circuits pp. C272 - C273 |
---|---|
Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
JSAP
01.06.2019
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE) and half-rate 10-tap decision feedback equalizer (DFE) with first tap speculative. Proposed voltage pre-shift scheme uses a programmable offset added on top of the differential data signal to alleviate front end nonlinearity. The receiver achieves BER \lt 1 \mathrm { E } - 8 at optimal timing pre-FEC and 0.2UI at 1E-6 BER over 25dB insertion loss at 14GHz. The test-chip consumes 450mW under 1.0V/1.2V power supplies, giving a FoM of 0.321pJ/bit/dB. The active area is 0.352mm 2 . |
---|---|
AbstractList | A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE) and half-rate 10-tap decision feedback equalizer (DFE) with first tap speculative. Proposed voltage pre-shift scheme uses a programmable offset added on top of the differential data signal to alleviate front end nonlinearity. The receiver achieves BER \lt 1 \mathrm { E } - 8 at optimal timing pre-FEC and 0.2UI at 1E-6 BER over 25dB insertion loss at 14GHz. The test-chip consumes 450mW under 1.0V/1.2V power supplies, giving a FoM of 0.321pJ/bit/dB. The active area is 0.352mm 2 . |
Author | Tsai, Chien-Chun Huang, Wen-Hung Yang, Shu-Chun Chen, Wei-Chih Hsieh, Kenny Cheng-Hsiang Shih, Yu-Nan |
Author_xml | – sequence: 1 givenname: Wei-Chih surname: Chen fullname: Chen, Wei-Chih organization: TSMC, Hsinchu, Taiwan – sequence: 2 givenname: Shu-Chun surname: Yang fullname: Yang, Shu-Chun organization: TSMC, Hsinchu, Taiwan – sequence: 3 givenname: Yu-Nan surname: Shih fullname: Shih, Yu-Nan organization: TSMC, Hsinchu, Taiwan – sequence: 4 givenname: Wen-Hung surname: Huang fullname: Huang, Wen-Hung organization: TSMC, Hsinchu, Taiwan – sequence: 5 givenname: Chien-Chun surname: Tsai fullname: Tsai, Chien-Chun organization: TSMC, Hsinchu, Taiwan – sequence: 6 givenname: Kenny Cheng-Hsiang surname: Hsieh fullname: Hsieh, Kenny Cheng-Hsiang organization: TSMC, Hsinchu, Taiwan |
BookMark | eNotkM1OwkAURkejiRR9Ajb3BQbmtzOzJBWQpEYiyJaM7R0ZA1PSVo1vL4msvpOzOIsvIzepSUjIiLOxkI67ybZcL4uxYNyNrTHGOXFFMmVzqawRzFyTgeDaUp3L_I5kXffJmNBc6AHBKeh88T7pYDV9pgpescL4jS38xH4P2-bQ-w-EVYt0vY-hh2JTzsCnGjijG3-Cx_kMmgBnpBzWJ6y-Dr6PTYKYwKQjzGOazzb35Db4Q4cPlx2St7Mtnmj5slgW05JGbnRPUWDlkPPKKW1CVXNnnGbMM6VVEKidlXlQylrkEmurQo1S5t6IwK2oVJBDMvrvRkTcndp49O3v7nKJ_ANO7lMa |
ContentType | Conference Proceeding |
DBID | 6IE 6IH CBEJK RIE RIO |
DOI | 10.23919/VLSIC.2019.8777992 |
DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Xplore IEEE Proceedings Order Plans (POP) 1998-present |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Xplore url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering |
EISBN | 4863487207 9784863487208 |
EISSN | 2158-5636 |
EndPage | C273 |
ExternalDocumentID | 8777992 |
Genre | orig-research |
GroupedDBID | 29G 6IE 6IF 6IH 6IK 6IL 6IM 6IN AAJGR ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP IPLJI JC5 OCL RIE RIL RIO |
ID | FETCH-LOGICAL-i175t-e2ec9e11c9457fcd1979500a0454f2e59836f4488e13ed84fde336a72f182c4f3 |
IEDL.DBID | RIE |
IngestDate | Wed Jun 26 19:29:03 EDT 2024 |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-i175t-e2ec9e11c9457fcd1979500a0454f2e59836f4488e13ed84fde336a72f182c4f3 |
ParticipantIDs | ieee_primary_8777992 |
PublicationCentury | 2000 |
PublicationDate | 2019-June |
PublicationDateYYYYMMDD | 2019-06-01 |
PublicationDate_xml | – month: 06 year: 2019 text: 2019-June |
PublicationDecade | 2010 |
PublicationTitle | 2019 Symposium on VLSI Circuits |
PublicationTitleAbbrev | VLSIC |
PublicationYear | 2019 |
Publisher | JSAP |
Publisher_xml | – name: JSAP |
SSID | ssj0025125 |
Score | 1.7799214 |
Snippet | A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE)... |
SourceID | ieee |
SourceType | Publisher |
StartPage | C272 |
SubjectTerms | Bandwidth Clocks Decision feedback equalizers FinFETs Latches Receivers Timing |
Title | A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET |
URI | https://ieeexplore.ieee.org/document/8777992 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3JTsMwELUKJ7iwi11z4IjbeElSH1FpWdQiJNqqtyqJx6IC0grSC1_POCllEQcukRUpseWxZvzsmfcYOwu0CNIwjXmmXcS1xIQbLTXPLC1mihAJljpkvbvoeqBvR-Goxs6XtTCIWCafYd03y7t8O83m_qis4bnrjCGHu9IMZFWrtQRXFLjCilVIKiNMY9h9uGn51C1aC9VnP_RTyvDR2WC9z46rrJGn-rxI69n7L07G_45sk-1-FerB_TIEbbEa5tts_RvH4A7DCwijq7TxBvcXPa6B9onoczHAn8DCcPpckEehnyB_eJy4Alr9bhuS3AJ5zn4yg8tOG6YOqMkFeLX6hd4XTHKI8xfoTPJOu7_LBvRsXfOFtgKf0Iah4CgxMyhEZnQYu8wKE5swCBLPyOckhqapIkfQrYlCoW1qZ1GpKImlI0BCdlV7bDWf5rjPQLtYWkuwLVVGp6E1UaKUkCkB3kQYGxywHT9h41lFnzFezNXh36-P2Jo3WpWNdcxWi9c5nlDcL9LT0uAfAxCoxw |
link.rule.ids | 310,311,786,790,795,796,802,23958,23959,25170,27958,55109 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV07T8MwELZQGYCFt3hzAyNu49hJ6hGVlgItQmqLulVJfBYVkFaQLvx6zkkpDzGwRFakPOSz7rvPvvuOsTNPCS8JkoinyoZc-RhzrXzFU0OLmRAixqIPWfcubA_UzTAYLrHzRS0MIhbJZ1h1w-Is30zSmdsqqzntOq3J4S4Tznu6rNZa0CuCrqDUFfKlFrr20OldN1zyFq2G8sEfHVQKAGmts-7np8u8kafqLE-q6fsvVcb__tsG2_kq1YP7BQhtsiXMttjaN5XBbYYXEIRXSe0N7i-6XAFFiuiyMcDtwcLD5Dknn0IvQd57HNscGv1OE-LMAPnOfjyFy1YTJhZoyAW4fvXzjl8wziDKXqA1zlrN_g4b0LXR5vPuCnxMIUPO0cdUoxCpVkFkUyN0pAPPi50mn_Ux0HUZWiJvdRQSTV1Zg1KGceRboiRkWbnLKtkkwz0Gyka-MUTcEqlVEhgdxlIKPyHKGwttvH227SZsNC0FNEbzuTr4-_YpW2n3u51R5_ru9pCtOgOWuVlHrJK_zvCYooA8OSmM_wEf_Kwd |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=2019+Symposium+on+VLSI+Circuits&rft.atitle=A+56Gb%2Fs+PAM-4+Receiver+with+Voltage+Pre-Shift+CTLE+and+10-Tap+DFE+of+Tap-1+Speculation+in+7nm+FinFET&rft.au=Chen%2C+Wei-Chih&rft.au=Yang%2C+Shu-Chun&rft.au=Shih%2C+Yu-Nan&rft.au=Huang%2C+Wen-Hung&rft.date=2019-06-01&rft.pub=JSAP&rft.eissn=2158-5636&rft.spage=C272&rft.epage=C273&rft_id=info:doi/10.23919%2FVLSIC.2019.8777992&rft.externalDocID=8777992 |