A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET

A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE) and half-rate 10-tap decision feedback equalizer (DFE) with first tap speculative. Proposed voltage pre-shift scheme uses a programmable offs...

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Bibliographic Details
Published in2019 Symposium on VLSI Circuits pp. C272 - C273
Main Authors Chen, Wei-Chih, Yang, Shu-Chun, Shih, Yu-Nan, Huang, Wen-Hung, Tsai, Chien-Chun, Hsieh, Kenny Cheng-Hsiang
Format Conference Proceeding
LanguageEnglish
Published JSAP 01.06.2019
Subjects
Bandwidth
Clocks
Decision feedback equalizers
FinFETs
Latches
Receivers
Timing
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Summary:A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE) and half-rate 10-tap decision feedback equalizer (DFE) with first tap speculative. Proposed voltage pre-shift scheme uses a programmable offset added on top of the differential data signal to alleviate front end nonlinearity. The receiver achieves BER \lt 1 \mathrm { E } - 8 at optimal timing pre-FEC and 0.2UI at 1E-6 BER over 25dB insertion loss at 14GHz. The test-chip consumes 450mW under 1.0V/1.2V power supplies, giving a FoM of 0.321pJ/bit/dB. The active area is 0.352mm 2 .
ISSN:2158-5636
DOI:10.23919/VLSIC.2019.8777992