A new design technique of hybrid SET/CMOS static memory cells

• Published in: 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003 Vol. 2; pp. 674 - 677 vol. 2
• Main Authors: Bong-Hoon Lee, Yoon-Ha Jeong
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: CMOS memory circuits; CMOS technology; Electrons; Energy consumption; Fabrication; MOSFET circuits; Nanoscale devices; Read-write memory; Tunneling; Voltage
• ISBN: 0780379764; 9780780379763
• DOI: 10.1109/NANO.2003.1231002

The single electron transistor(SET)/CMOS-based static memory cell is proposed. The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks having the NDC. The peak-to-valley current ratio of the SET block is above 5 with C/sub G/=5.4C/sub T/(C/sub T/=0.1aF) at T=77K. A read and write operation of the proposed memory cell was validated with SET/CMOS hybrid simulation at T=77K. Even though the fabrication process which integrate MOSFET devices and SET block with NDC is not available, these results suggest that the proposed SET/CMOS static memory cell is suitable for a high density memory system with the low power consumption.